Lisbon, Portugal Accelerated Validation Group
About the job Design Verification Engineer
ADVANS Portugal is looking for experienced Design Verification Engineersto our new Lisbon offices.
This is a full-time hybrid role, with flexibility for remote work.
Key Responsibilities / Duties:
- Develop and execute verification plans based on design specifications.
- Create testbenches and test cases using SystemVerilog/UVM or equivalent tools.
- Perform simulations and debug design issues in collaboration with design teams.
- Conduct functional, regression, and coverage testing to ensure design correctness.
- Analyze coverage metrics and enhance test cases to meet verification goals.
- Document test procedures, results, and track issues through resolution.
Qualification Requirements:
- BSc or MSc in Computer Science, Electronics, Automation or related software disciplines
- 3+ years of experience in digital verification, with expertise in UVM/SystemVerilog or Specman/e.
- Proficiency in system architecture including processor architecture.
- Experience in debugging Gate-Level Simulations (GLS) and timing closure.
- Solid understanding of C/C++ and familiarity with scripting tools (Python, Perl, Tcl).
- Integration program in a professional, young & dynamic team
#J-18808-Ljbffr