P Digital IC / ASIC / EIC Engineer (Onsite – Portugal)p Location: Aveiro District, Portugal (Onsite) /pp Salary: €40,000 – €50,000 (flexible for exceptional candidates) /pp Experience Level: Mid-level /pp About the Opportunity /pp We are partnering with an innovative semiconductor and hardware technology company at the forefront of advanced integrated circuit design.
They are seeking a Digital IC / ASIC / EIC Engineer to join their growing engineering team, working on cutting-edge chip development projects across a range of industries.
/pp This is a fantastic opportunity to contribute to complex ASIC and SoC programs within a highly collaborative, technically driven environment.
/pp Key Responsibilities /pulli Design and develop digital circuits for ASIC / SoC platforms /lili Define and implement RTL architecture and micro-architecture (Verilog / SystemVerilog / VHDL) /lili Deliver block-level and top-level designs, including datapath, control logic, interfaces, and peripherals /lili Perform RTL simulations and validation /lili Carry out gate-level synthesis, including: /lili Static Timing Analysis (STA) /lili Constraint definition and validation /lili Conduct Lint analysis and Logic Equivalence Checking (LEC) /lili Support low-power design and optimisation strategies /lili Collaborate closely with verification and physical design teams across ASIC programs /li /ulp? Required Skills Experience /pulli Experience in digital IC, ASIC, or SoC design /lili RTL design (Verilog / SystemVerilog / VHDL) /lili ASIC design flow and methodologies /lili Synthesis, timing analysis, and constraint management /lili Debugging and verification processes /lili Familiarity with EDA toolchains (Cadence, Synopsys, or Mentor Graphics) /li /ulp Technical Stack /pulli Hardware Description Languages: SystemVerilog, Verilog, VHDL /lili Scripting: Python, TCL, Perl /lili Tools Environment: /lili Cadence / Synopsys / Mentor (front-end flow) /lili Git, Linux, scripting environments /li /ulp Nice to Have /pulli Knowledge of Design for Test (DfT) /lili Experience with low-power design techniques /li /ulp Why Apply?
/pulli Work on advanced semiconductor technologies /lili Join a highly skilled and collaborative engineering team /lili Clear opportunity to grow within complex ASIC development programmes /li /ul /p